With the advance in miniaturization of semiconductors, future semiconductor integrated circuits are expected to have mounted thereon a large number of cores such as CPU, processing circuits and the like. However, the test times for a semiconductor integrated circuit becomes longer as the number of cores increases more and more, as a matter of course. To reduce test times, it is essential to accomplish both collective testing of a plurality of cores in parallel and testing of cores under test in various orders.
FIG. 1 is a schematic diagram showing an exemplary configuration of a related semiconductor integrated circuit.
The example shown in FIG. 1 is provided with a plurality of scan chains 20010P1˜Pn and compactor 20100. Compactor 20100 comprises an injector network 20110 for generating an intermediate value from the results of tests by plurality of scan chains 20010P1˜Pn, and memory element 20120 for storing the generated intermediate value. In this way, tests can be conducted in parallel in plurality of scan chains 20010P1˜Pn, so that the results of these tests can be compressed.
However, the example shown in FIG. 1 implies the following problem.
Since all of the scan chains must be utilized together, a particular core alone cannot be tested, or a particular scan chain alone cannot test cores.
There is an information processing apparatus as described in Patent Document 1, as a technique comparable to the foregoing. Patent Document 1 discloses a compactor, similar to the example shown in FIG. 1. Accordingly, the technique described in Patent Document 1 implies the same problem as the example shown in FIG. 1.
FIG. 2 is a schematic diagram showing another exemplary configuration of a related semiconductor integrated circuit.
The example shown in FIG. 2 is provided with a plurality of scan chains 30010P1˜Pn connected to a plurality of cores 30020P1˜Pn, respectively. The example is further provided with core switching unit 30100 for switching inputs to the plurality of scan chains 30010P1˜Pn, and a switching control unit 30200 for controlling core switching unit 30100. In this way, a particular core alone can be tested among a plurality of cores 30020P1˜Pn.
However, the example shown in FIG. 2 implies the following problem.
Due to connections through the switching unit, the connections of the scan chains are previously fixed, so that flexible tests cannot be conducted according to a load, such as a change in the order of testing cores, grouping of cores under test, and the like.
There is an information processing apparatus as described in Patent Document 2, as a technique comparable to the foregoing. Patent Document 2 discloses integrated circuit switching means equivalent to the core switching unit, similar to the example shown in FIG. 2. Accordingly, the technique described in Patent Document 2 implies the same problem as the example shown in FIG. 2.
FIG. 3 is a schematic diagram showing a further exemplary configuration of a related semiconductor integrated circuit.
The example shown in FIG. 3 is provided with an inter-connection network 10200 comprised of routers 10100A and 10100B, and master core 10010 and slave core 10020 are connected through this inter-connection network 10200. In this way, since the connection between master core 10010 and slave core 10020 is virtualized through network-based coupling, the two parts can be connected by way of various paths.
However, the example shown in FIG. 3 implies the following problem.
Though supporting communications between the cores, the example does not at all consider a test for the connected cores.
There is an information processing apparatus as described in Patent Document 3 as a technique comparable to the foregoing. Patent Document 3 discloses an inter-connection network, similar to the example shown in FIG. 3. Accordingly, the technique described in Patent Document 3 implies the same problem as the example shown in FIG. 3.
As described above, in a semiconductor integrated circuit comprising a plurality of cores connected to an inter-connection network, in order to accommodate an increased number of cores resulting from increased miniaturization of semiconductors, it is necessary to reconcile both collective testing of a plurality of cores in parallel, and testing of cores under test in various orders, but a problem arises in that the reconcilement is difficult to achieve with the related techniques described above.    Patent Document 1: JP-2006-518855A    Patent Document 2: Japanese Patent No. 3791859    Patent Document 3: JP-2006-502487A